Changes between Version 10 and Version 11 of AnnPerformance

Timestamp:

05/13/08 12:54:02 (15 years ago)

Author:

hartono

Comment:

--

AnnPerformance

@@ -3 +3 @@
 == Platform ==
 All results were obtained from using a quad-core Intel Core 2 Quad Q6600 CPU clocked at 2.4 Ghz with 32 KB L1 D cache, 8MB of L2 cache (4MB shared per core pair), and 2 GB of DDR2-667 RAM, running Linux kernel version 2.6.22 (x86-64). The compiler used was ICC 10.1.
+
+== Optimizations used ==
+We used PLuTo (an auto-parallelization and locality optimization tool based on polyhedral models) as a polyhedral-based code transformator. And we also extended ancc with additional modules used to perform syntactical transformations. Below are the (polyhedral and syntactic) optimizations used in this experiment.
+
+''Polyhedral'' transformations (from PLuTo):
+ * Loop tiling for L1 and L2 caches
+ * Loop fusion
+ * Parallelization for multicore machines
+ * Register tiling (for rectangular iteration spaces)
+
+''Syntactic'' transformations (from ancc modules):
+ * Register tiling (for both rectangular and non-rectangular iteration spaces)
+ * Loop permutation/interchange
+ * Scalar replacement (to enhance register reuse)
+ 
+It is to be noted that the register tiling approach used by PLuTo is limited to only rectangular loops. To further improve the resulting performance, we implemented our own register tiling approach as one of the ancc's transformation modules. Our register tiling approach is so general that it can handle both rectangular and non-rectangular loops.
 
 == LU Decomposition ==
@@ -18 +34 @@
 }}}
 
-=== Optimizations used ===
-We used PLuTo (an auto-parallelization and locality optimization tool based on polyhedral models) as a polyhedral-based code transformator. And we also extended ancc with additional modules used to perform syntactical transformations. Below are the (polyhedral and syntactic) optimizations used in this experiment.
-
-''Polyhedral'' transformations (from PLuTo):
- * Loop tiling for L1 and L2 caches
- * Parallelization for multicore machines
- * Register tiling (for rectangular iteration spaces)
-
-''Syntactic'' transformations (from ancc modules):
- * Register tiling (for both rectangular and non-rectangular iteration spaces)
- * Loop permutation/interchange
- * Scalar replacement (to enhance register reuse)
- 
-It is to be noted that the register tiling approach used by PLuTo is limited to only rectangular loops. To further improve the resulting performance, we implemented our own register tiling approach as one of the ancc's transformation modules. Our register tiling approach is so general that it can handle both rectangular and non-rectangular loops.
-
 === Sequential (single core) ===
  [[Image(lu.png,nolink)]]